NXP Semiconductors /MIMXRT1064 /IOMUXC_GPR /GPR1

SAI1 MCLK1 source select

0 (SAI1_MCLK1_SEL_0): ccm.ssi1_clk_root

1 (SAI1_MCLK1_SEL_1): ccm.ssi2_clk_root

2 (SAI1_MCLK1_SEL_2): ccm.ssi3_clk_root

3 (SAI1_MCLK1_SEL_3): iomux.sai1_ipg_clk_sai_mclk

4 (SAI1_MCLK1_SEL_4): iomux.sai2_ipg_clk_sai_mclk

5 (SAI1_MCLK1_SEL_5): iomux.sai3_ipg_clk_sai_mclk

SAI1 MCLK2 source select

0 (SAI1_MCLK2_SEL_0): ccm.ssi1_clk_root

1 (SAI1_MCLK2_SEL_1): ccm.ssi2_clk_root

2 (SAI1_MCLK2_SEL_2): ccm.ssi3_clk_root

3 (SAI1_MCLK2_SEL_3): iomux.sai1_ipg_clk_sai_mclk

4 (SAI1_MCLK2_SEL_4): iomux.sai2_ipg_clk_sai_mclk

5 (SAI1_MCLK2_SEL_5): iomux.sai3_ipg_clk_sai_mclk

SAI1 MCLK3 source select

0 (SAI1_MCLK3_SEL_0): ccm.spdif0_clk_root

1 (SAI1_MCLK3_SEL_1): iomux.spdif_tx_clk2

2 (SAI1_MCLK3_SEL_2): spdif.spdif_srclk

3 (SAI1_MCLK3_SEL_3): spdif.spdif_outclock

SAI2 MCLK3 source select

0 (SAI2_MCLK3_SEL_0): ccm.spdif0_clk_root

1 (SAI2_MCLK3_SEL_1): iomux.spdif_tx_clk2

2 (SAI2_MCLK3_SEL_2): spdif.spdif_srclk

3 (SAI2_MCLK3_SEL_3): spdif.spdif_outclock

SAI3 MCLK3 source select

0 (SAI3_MCLK3_SEL_0): ccm.spdif0_clk_root

1 (SAI3_MCLK3_SEL_1): iomux.spdif_tx_clk2

2 (SAI3_MCLK3_SEL_2): spdif.spdif_srclk

3 (SAI3_MCLK3_SEL_3): spdif.spdif_outclock

Global interrupt “0” bit (connected to ARM M7 IRQ#0 and GPC)

0 (GINT_0): Global interrupt request is not asserted.

1 (GINT_1): Global interrupt request is asserted.

ENET1 reference clock mode select.

0 (ENET1_CLK_SEL_0): ENET1 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function.

1 (ENET1_CLK_SEL_1): Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller.

ENET2 reference clock mode select.

0 (ENET2_CLK_SEL_0): ENET2 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET2_REF_CLK function.

1 (ENET2_CLK_SEL_1): Gets ENET2 TX reference clock from the ENET2_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller.

USB Exposure mode

0 (USB_EXP_MODE_0): Exposure mode is disabled.

1 (USB_EXP_MODE_1): Exposure mode is enabled.

ENET1_TX_CLK data direction control

0 (ENET1_TX_CLK_DIR_0): ENET1_TX_CLK output driver is disabled

1 (ENET1_TX_CLK_DIR_1): ENET1_TX_CLK output driver is enabled

ENET2_TX_CLK data direction control

0 (ENET2_TX_CLK_DIR_0): ENET2_TX_CLK output driver is disabled

1 (ENET2_TX_CLK_DIR_1): ENET2_TX_CLK output driver is enabled

sai1.MCLK signal direction control

0 (SAI1_MCLK_DIR_0): sai1.MCLK is input signal

1 (SAI1_MCLK_DIR_1): sai1.MCLK is output signal

sai2.MCLK signal direction control

0 (SAI2_MCLK_DIR_0): sai2.MCLK is input signal

1 (SAI2_MCLK_DIR_1): sai2.MCLK is output signal

sai3.MCLK signal direction control

0 (SAI3_MCLK_DIR_0): sai3.MCLK is input signal

1 (SAI3_MCLK_DIR_1): sai3.MCLK is output signal

Exclusive monitor response select of illegal command

0 (EXC_MON_0): OKAY response

1 (EXC_MON_1): SLVError response (default)

ENET and ENET2 ipg_clk_s clock gating enable

0 (ENET_IPG_CLK_S_EN_0): ipg_clk_s is gated when there is no IPS access

1 (ENET_IPG_CLK_S_EN_1): ipg_clk_s is always on

ARM CM7 platform AHB clock enable

0 (CM7_FORCE_HCLK_EN_0): AHB clock is not running (gated)

1 (CM7_FORCE_HCLK_EN_1): AHB clock is running (enabled)